<h1 id="mission">mission</h1>
<ul>
<li>raise level of design</li>
<li>accelerate design loop</li>
<li>realize true reconfigurable hardware dream</li>
<li>disrupt vlsi industry</li>
</ul>
<h1 id="chisel">chisel</h1>
<ul>
<li>llvm for hardware
<ul>
<li>stanza chisel -- chipper?</li>
<li>verilog to flo to verilog</li>
<li>auto fame</li>
<li>auto microarchitecture -&gt; auto rate balancing</li>
</ul></li>
<li>fast parallel simulation
<ul>
<li>island finder</li>
<li>utl based</li>
</ul></li>
<li>risc-v / chisel tensilica
<ul>
<li>chisel -&gt; spike plug in</li>
<li>add C support for coprocessor instructions</li>
</ul></li>
<li>debugging tools
<ul>
<li>hardware visualization</li>
<li>interactive debugging</li>
<li>fast snapshotting everywhere</li>
</ul></li>
<li>fault injection
<ul>
<li>get basic support going</li>
<li>use statistics to reduce simulation time</li>
</ul></li>
<li>power modeling
<ul>
<li>sample based modeling</li>
<li>rtl estimation</li>
</ul></li>
<li>dsp / analog modeling support
<ul>
<li>audio library</li>
<li>systemverilog real support</li>
</ul></li>
<li>chiselization of x
<ul>
<li>multimedia</li>
<li>spatial computing</li>
</ul></li>
<li>component library
<ul>
<li>build out basic components -- soc -- sdr -- dsp</li>
<li>jar file support</li>
<li>website</li>
</ul></li>
<li>systemC integration
<ul>
<li>get chisel to output systemC models</li>
<li>support sst</li>
</ul></li>
<li>support for asics
<ul>
<li>floor planning</li>
<li>power gating</li>
</ul></li>
</ul>
<h1 id="declarative-design">declarative design</h1>
<ul>
<li>incrementally higher levels
<ul>
<li>sw/hw language -- accelerator interface -- higher level ops</li>
<li>transactors -- datapath on side</li>
<li>state machine combinators</li>
</ul></li>
<li>arduino for fpgas
<ul>
<li>fast streaming</li>
<li>exposed control / status registers -- wishbone type network</li>
<li>robotics</li>
<li>radio astronomy</li>
</ul></li>
<li>design space exploration
<ul>
<li>visualization</li>
<li>interactive gui</li>
<li>declarative specifications</li>
</ul></li>
<li>generalization to
<ul>
<li>solids</li>
<li>electro mechanical systems</li>
</ul></li>
</ul>
<h1 id="dreamer">dreamer</h1>
<ul>
<li>network
<ul>
<li>separate network processor</li>
<li>circuit switched</li>
<li>hierarchical</li>
</ul></li>
<li>isa tuning
<ul>
<li>bit register file</li>
<li>lut instruction</li>
<li>permute instruction</li>
</ul></li>
<li>better scheduling
<ul>
<li>more merging network and compute</li>
<li>lock registers for named signals</li>
</ul></li>
<li>microarchitectural options
<ul>
<li>more pipelining</li>
<li>pay as you go execution</li>
<li>fine grained dynamic dataflow</li>
</ul></li>
<li>eda algorithms
<ul>
<li>graph balancing</li>
<li>sse</li>
<li>constant folding</li>
</ul></li>
<li>clustering
<ul>
<li>for threads</li>
<li>for luts</li>
</ul></li>
<li>other layout
<ul>
<li>tabu analytic</li>
<li>space time scheduling</li>
<li>parallelize layout</li>
<li>time guided layout</li>
</ul></li>
<li>dynamic hardware
<ul>
<li>hardware gas</li>
<li>jit compilation to hardware</li>
<li>dynamic layout + schedulign</li>
<li>never ending design -- maintained in hw --</li>
</ul></li>
<li>tape out
<ul>
<li>floor planning</li>
<li>clock islands</li>
<li>power gating</li>
<li>high speed io</li>
<li>rocc</li>
</ul></li>
<li>diablo II
<ul>
<li>scale out</li>
</ul></li>
</ul>
<h1 id="hurricane">hurricane</h1>
<ul>
<li>applications
<ul>
<li>fpga apps</li>
<li>compute vision</li>
<li>radio astronomy</li>
<li>sdr</li>
<li>robotics</li>
</ul></li>
<li>systolic
<ul>
<li>bring over algorithms and mapping strategies</li>
<li>hand optimize for baseline</li>
</ul></li>
<li>datapath design
<ul>
<li>short vectors</li>
<li>complex numbers</li>
<li>floating point</li>
</ul></li>
</ul>
